This invention relates to clocks, and more particularly to clocks for providing synchronizing signals.
Most integrated circuits are synchronous in operation and utilize at least one master clock and generate other clocks from that master clock. The generation of multiple clocks is for different purposes and different locations. The differing functions of the integrated circuit have different clocks for the particular purpose. For a processing system it is desirable that each cycle of the clock, a variety of options are available, such as performing any of the instructions in the instruction set of the processing system. The speed of the clock, while it is desirable that it be fast, must be slow enough to allow all of the operations necessary to complete an instruction to be completed. Some of the operations that are needed or are desirable relate to getting as many things done as possible in a single clock cycle. In order to do this, there must the needed clocks to achieve these results. One technique has been to double the clock frequency in order to provide the clocking necessary for these operations.
One disadvantage of this double frequency approach is that the need to provide a phase locked loop for it. The phase locked loop itself generally requires a voltage controlled oscillator (VCO). For proper operation, there is significant design resources and space on the integrated circuit that are required. The result is a time-consuming and space consuming approach.
Thus, there is a need for providing a clocking mechanism for operations during a cycle that does not require doubling the frequency with a phased locked loop.